View AD5235_479364.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
Nonvolatile Memory, Dual 1024-Position Digital Potentiometers AD5235*
FUNCTIONAL BLOCK DIAGRAM
ADDR DECODE
FEATURES Dual, 1024-Position Resolution 25 k , 250 k Nominal Resistance Low Temperature Coefficient: 35 ppm/ C Nonvolatile Memory1 Preset Maintains Wiper Settings Permanent Memory Write-Protection Wiper Settings Read Back Resistance Tolerance Stored in EEMEM1 Linear Increment/Decrement Log Taper Increment/Decrement SPI-Compatible Serial Interface 3 V to 5 V Single Supply or 2.5 V Dual Supply 26 Bytes User Nonvolatile Memory for Constant Storage 100-Year Typical Data Retention TA = 55 C APPLICATIONS SONET, SDH, ATM, Gigabit Ethernet DWDM Laser Diode Driver, Optical Supervisory Systems Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage to Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment Low Resolution DAC Replacement GENERAL DESCRIPTION
AD5235
RDAC1 REGISTER
VDD A1 W1
CS CLK SDI SDO PR WP RDY
SERIAL INTERFACE EEMEM1 POWER-ON PRESET EEMEM CONTROL EEMEM2 RDAC2 RDAC1
B1
RDAC2 REGISTER
A2 W2 B2
26 BYTES USER EEMEM
VSS GND
When changes are made to the RDAC register, the value of the new setting can be saved into the EEMEM. Thereafter, it will be transferred automatically to the RDAC register during system power ON, which is enabled by the internal preset strobe. EEMEM can also be retrieved through direct programming and external preset pin control. The linear step increment and decrement commands cause the setting in the RDAC register to be moved UP or DOWN, one step at a time. For logarithmic changes in wiper setting, a left/right bit shift command adjusts the level in 6 dB steps. The AD5235 is available in a thin TSSOP-16 package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C.
100
RWA(D), RWB(D) - % of Full-Scale RAB
The AD5235 provides a dual channel, digitally controlled digital potentiometer2 with resolution of 1024 positions. These devices perform the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. The AD5235's versatile programming via a standard serial interface allows 16 modes of operation and adjustment, including scratch pad programming, memory storing and retrieving, increment/decrement, log taper adjustment, wiper setting readback, and extra user-defined EEMEM. Another key feature of the AD5235 is that the actual resistance tolerance is stored in the EEMEM. The actual end-to-end resistance can therefore be known, which is valuable for calibration, tolerance matching and precision applications. In the scratch pad programming mode, a specific setting can be programmed directly to the RDAC2 register, which sets the resistance between terminals W-A and W-B. The RDAC register can also be loaded with a value previously stored in the EEMEM register. The value in the EEMEM can be changed or protected.
*Patent pending NOTES 1 The terms nonvolatile memory and EEMEM are used interchangeably. 2 The terms digital potentiometer and RDAC are used interchangeably.
RWA 75
RWB
50
25
0
0
256
512 CODE - Decimal
768
1023
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 1. (D) and RWB(D) vs. Decimal Code
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD5235-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, 25 k
Parameter Symbol
AND 250 k
Conditions
VERSIONS
Min Typ2 Max +2 +4 35 50 200 0.1 100 Unit LSB LSB ppm/ C % % Bits LSB LSB ppm/ C LSB LSB V pF pF 2 A V V V V V 0.5 4.9 0.4 2.25 5 V V V A pF V V A A mA mA A W %/%
(VDD = 3 V to 5.5 V, -40 C < TA < +85 C, unless otherwise noted.1)
DC CHARACTERISTICS-RHEOSTAT MODE Specifications Apply to All RDACs Resistor Differential Nonlinearity3 R-DNL RWB -2 R-INL RWB -4 Resistor Integral Nonlinearity3 Resistance Temperature Coefficient RAB /T Wiper Resistance RW VDD = 5 V, IW = 1 V/RWB, Code = 200H VDD = 3 V, IW = 1 V/RWB, Code = 200H Ch 1 and 2 RWB, Dx = 3 FFH Channel Resistance Matching RWB /RWB Nominal Resistor Tolerance RWB Dx = 3 FFH -30 DC CHARACTERISTICS-POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N 10 Differential Nonlinearity4 DNL -2 INL -4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient VW /T Code = Half Scale Full-Scale Error VWFSE Code = Full Scale -6 Zero-Scale Error VWZSE Code = Zero Scale 0 RESISTOR TERMINALS Terminal Voltage Range5 Capacitance6 Ax, Bx Capacitance6 Wx Common-Mode Leakage Current6, 7 DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High (SDO, RDY) Output Logic Low Input Current Input Capacitance6 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Positive Supply Current Programming Mode Current Read Mode Current8 Negative Supply Current Power Dissipation9 Power Supply Sensitivity6 VA, B, W CA, B CW ICM VIH VIL VIH VIL VIH VIL VOH VOL IIL CIL VDD VDD/VSS IDD IDD IDD(PG) IDD(XFR) ISS PDISS PSS VSS f = 1 MHz, measured to GND, Code = Half Scale f = 1 MHz, measured to GND, Code = Half Scale VW = VDD / 2 With respect to GND, VDD = 5 V With respect to GND, VDD = 5 V With respect to GND, VDD = 3 V With respect to GND, VDD = 3 V With respect to GND, VDD = +2.5 V, VSS = -2.5 V With respect to GND, VDD = +2.5 V, VSS = -2.5 V RPULL-UP = 2.2 k to 5 V IOL = 1.6 mA, VLOGIC = 5 V VIN = 0 V or VDD 2.4
+30
+2 +4 15 0 4 VDD 11 80 0.01
0.8 2.1 0.6 2.0
VSS = 0V VIH = VDD or VIL = GND, TA = 25 C VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = - 2.5 V VIH = VDD or VIL = GND VDD = 5 V 10%
3.0 2.25 2 3.5 35 3 3.5 18 0.002
5.5 2.75 4.5 6.0 9 6.0 50 0.01
0.3
-2-
REV. A
AD5235
Parameter DYNAMIC CHARACTERISTICS Bandwidth -3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Spectral Density Crosstalk (CW1/CW2) Analog Crosstalk
6, 10
Symbol BW THDW tS eN_WB CT CTA
Conditions VDD/VSS = 2.5 V, RAB = 25 k/250 k VA = 1 Vrms, VB = 0 V, f =1 kHz VA = VDD, VB = 0 V, VW = 0.50% Error Band, Code 000H to 200H, RAB = 25 k/250 k RAB = 25 k/250 k, TA = 25C VA = VDD, VB = 0 V, Measured VW1 with VW2 Making Full-Scale Change VDD = VA1 = +2.5 V, VSS = VB1 = - 2.5 V, Measure VW1 with VW2 = 5 V p-p @ f = 1 kHz, Code 1 = 200H, Code 2 = 3 FFH, RAB = 25 k/250 k
6, 11
Min Typ2 125/12 0.05 4/36 20/64 90/21
Max
Unit kHz % s nV/Hz nV-s
-81/-62 20 10 1 10 5 5 40 50 50 10 4 0 0.15 30 10 50 140 100 100 0.3
dB ns ns tCYC ns ns ns ns ns ns ns tCYC ns ms ms ns ns s K Cycles Years
INTERFACE TIMING CHARACTERISTICS Applies to All Parts Clock Cycle Time (tCYC) t1 CS Setup Time t2 CLK Shutdown Time to CS Rise t3 Input Clock Pulsewidth t4, t5 Clock Level High or Low Data Setup Time t6 From Positive CLK Transition Data Hold Time t7 From Positive CLK Transition CS to SDO-SPI Line Acquire t8 CS to SDO-SPI Line Release t9 CLK to SDO Propagation Delay12 t10 RP = 2.2 k, CL < 20pF t12 CS High Pulsewidth13 CS High to CS High13 t13 RDY Rise to CS Fall t14 CS Rise to RDY Fall Time t15 Read/Store to Nonvolatile EEMEM14 t16 Applies to Command 2H, 3H, 9H CS Rise to Clock Rise/Fall Setup t17 Preset Pulsewidth (Asynchronous) tPRW Not Shown in Timing Diagram Preset Response Time to tPRESP PR Pulsed Low to Refreshed Wiper Setting Wiper Positions FLASH/EE MEMORY RELIABILITY Endurance15 Data Retention16
NOTES 1 Parts can be operated at 2.7 V single supply, except from 0 C to -40 C where minimum 3 V is needed. 2 Typicals represent average readings at 25 C and VDD = 5 V. 3 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. I W ~ 50 mA for VDD = 2.7 V and IW ~ 400 mA for VDD = 5 V. See Test Circuit 1. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V DD and VB = V SS. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Test Circuit 2. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. Dual -supply operation enables ground referenced bipolar ac signal adjustment. 6 Guaranteed by design and not subject to production test. 7 Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V DD/2. 8 Transfer (XFR) mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 19. 9 PDISS is calculated from (I DD VDD) + (ISS VSS). 10 All dynamic characteristics use V DD = +2.5 V and V SS = -2.5 V. 11 See Timing Diagrams for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V DD = 3 V and 5 V. 12 Propagation delay depends on value of V DD, RPULL_UP, and CL. 13 Valid for commands that do not activate the RDY pin. 14 RDY pin low only for commands 2, 3, 8, 9, 10, and PR software pulse: CHD_8 ~ 1 ms; CHD_9, 10 ~ 0.1 ms; CHD_2, 3 ~ 20 ms. Device operational at T A = -40 C and VDD < 3 V extends the save time to 35 ms. 15 Endurance is qualified to 100,000 cycles as per JEDEC Standard 22, Method A117 and measured at -40 C, +25 C, and +85 C. Typical endurance at +25 C is 700,000 cycles. 16 Retention lifetime equivalent at junction temperature (T J) = 55 C as per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 V derates with junction temperature in the Flash/EE memory. See General Description section. Specifications subject to change without notice. The AD5235 contains 16,000 transistors. Die size: 99 mil 103 mil, 10,197 square mil.
REV. A
-3-
AD5235
TIMING DIAGRAMS
CS CPHA = 1
t12 t3 t2
CLK CPOL = 1
t13
t1 t5 t4 t10 t17 t11
LSB OUT
t8
SDO
t9
*
MSB
t7 t6
SDI MSB LSB
t14
RDY
t15 t16
*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED. THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2a. CPHA = 1 Timing Diagram
CS
CPHA = 0
t12 t1 t2
CLK CPOL = 0
t3 t5 t17
t13
t4
t8
SDO MSB OUT
t10
t11
LSB
t9
*
t7 t6
SDI MSB IN LSB
t14
RDY
t15 t16
*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED. THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2b. CPHA = 0 Timing Diagram
-4-
REV. A
AD5235
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VA, VB, VW to GND . . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V IA, IB, IW Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Digital Inputs and Output Voltage to GND . . -0.3 V, VDD + 0.3 V Operating Temperature Range3 . . . . . . . . . . . -40C to +85C Maximum Junction Temperature (TJ MAX) . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
Thermal Resistance Junction-to-Ambient JA TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C/W Thermal Resistance Junction-to-Case JC TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28C/W Package Power Dissipation = (TJ MAX - TA)/JA
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3 Includes programming of nonvolatile memory.
ORDERING GUIDE
Model AD5235BRU25 AD5235BRU25-RL7 AD5235BRU250 AD5235BRU250-RL7 AD5235EVAL25 AD5235EVAL250
RWB_FS k 25 25 250 250 25 250
RDNL 2 2 2 2
RINL 4 4 4 4
Temperature Package Range (C) Description -40 to +85 -40 to +85 -40 to +85 -40 to +85 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16
Package Option RU-16 RU-16 RU-16 RU-16
Ordering Quantity 96 1,000 96 1,000 1 1
Top Mark* 5235B25 5235B25 5235BD 5235BD
*Line 1 contains ADI logo symbol and date code YYWW, line 2 branding contains differentiating detail by part type.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5235 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-5-
AD5235
PIN CONFIGURATION
CLK 1 SDI 2 SDO 3 GND 4 VSS 5 A1 6 W1 7 B1 8
16 RDY 15 CS 14 PR
AD5235BRU
TOP VIEW (Not To Scale)
13 WP 12 VDD 11 A2 10 W2 9
B2
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3
Mnemonic CLK SDI SDO
Description Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loads first. Serial Data Output Pin. Open-drain output requires external pull-up resistor. CMD_9 and CMD_10 activate the SDO output. See Table II, Command Operation Truth Table. Other commands shift out the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of multiple packages. Ground Pin, Logic Ground Reference Negative Supply. Connect to 0 V for single-supply applications. A Terminal of RDAC1 Wiper Terminal of RDAC1. ADDR(RDAC1) = 0H. B Terminal of RDAC1 B Terminal of RDAC2 Wiper Terminal of RDAC2. ADDR(RDAC2) = 1H. A Terminal of RDAC2 Positive Power Supply Pin Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR strobe. CMD_1 and CMD_8 will refresh the RDAC register from EEMEM. Execute a NOP command before returning to WP high. Hardware Override of Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default to midscale 51210 until EEMEM loaded with a new value by the user (PR is activated at the logic high transition). Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. Ready. Active-high open-drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR.
4 5 6 7 8 9 10 11 12 13
GND VSS A1 W1 B1 B2 W2 A2 VDD WP
14
PR
15 16
CS RDY
-6-
REV. A
Typical Performance Characteristics- AD5235
1.0 0.8 0.6
R-DNL ERROR - LSB INL ERROR - LSB
+25 C -40 C +85 C
0.4
+25 C -40 C +85 C
0.2
0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
0.0
-0.2
-0.4
-0.6
-0.8
0
200
400
600
800
1000
0
200
DIGITAL CODE
400 600 DIGITAL CODE
800
1000
TPC 1. INL vs. Code, TA = 40 C, 85 C Overlay, RAB = 25 k
1.0 0.8 0.6 0.4
25 C,
TPC 4. R-DNL vs. Code, TA = 85 C Overlay, RAB = 25 k
70
40 C,
25 C,
POTENTIOMETER MODE TEMPCO - ppm/ C
+25 C -40 C +85 C
60 50 25k 40 250k 30 20 10 0 -10 -20 -30 0 128 256 384 512 640 VERSION VERSION
VDD /VSS = 5V/0V TA = 25 C
DNL ERROR - LSB
0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 0 200 400 600 800 1000
768
896
1023
DIGITAL CODE
CODE - Decimal
TPC 2. DNL vs. Code, TA = 40 C, 85 C Overlay, RAB = 25 k
1.0 0.8 0.6
25 C,
TPC 5. VWB /T Potentiometer Mode Tempco
RHEOSTAT MODE TEMPCO - ppm/ C
+25 C -40 C +85 C
120 100 80 60 40 20 0 -20 25k -40 250k -60 VERSION VERSION VDD /VSS = 5V/0V TA = 25 C
RINL ERROR - LSB
0.4 0.2 0.0 -0.2 -0.4 -0.6
0
200
400
600
800
1000
-80 0 128 256 384 512 640 768 896 1023 CODE - Decimal
DIGITAL CODE
TPC 3. RINL vs. Code, TA = 40 C, 85 C Overlay, RAB = 25 k
25 C,
TPC 6. RWB /T Rheostat Mode Tempco
REV. A
-7-
AD5235
36 34 32 30 28 Ohms 26 24 22 20
0.04 0.28
VDD = 3V VSS = 0V TA = 25 C
0.24
VDD /VSS = 2.5V VA = 1V RMS
0.20
THD + NOISE - %
RAB = 250k 0.16
0.12 25k 0.08
18 16 0 200 400 600 CODES 800 1.0k 1.2k
0.00 0.01k 0.1k 1k FREQUENCY - Hz 10k 100k
TPC 7. Wiper ON Resistance vs. Code
4
TPC 10. Total Harmonic Distortion vs. Frequency
3
3 IDD @ V DD/V SS = 5V/0V
CURRENT - A GAIN - dB
0 RAB =25k -3 RAB = 250k
2
f-3dB = 12kHz
-6
1 ISS @ V DD/V SS = 5V/0V
f-3dB = 125kHz
0 IDD @ V DD/V SS = 2.7V/0V ISS @ V DD/V SS = 2.7V/0V -1 -40 -20 0 20 40 60 80 100 -12 1k -9 VDD/V SS = 2.5V VA = 1V RMS D = MIDSCALE 10k 100k FREQUENCY - Hz 1M
TEMPERATURE - C
TPC 8. IDD vs. Temperature, RAB = 25 k
TPC 11. -3 dB Bandwidth vs. Resistance (Test Circuit 7)
0 CODE 200H
0.25 VDD/V SS = 5V/0V RAR = 25k 0.20 MIDSCALE FULL SCALE
-10
100H 080H
-20
ZERO SCALE
GAIN - dB
IDD - mA
0.15
040H 020H 010H
-30
0.10
-40
0.05
008H 004H 002H
-50 001H
0.00 0.0E+00
2.0E+06
4.0E+06
6.0E+06
8.0E+06
1.0E+07
1.2E+07
-60 1k
10k
100k FREQUENCY - Hz
1M
FREQUENCY - Hz
TPC 9. IDD vs. Clock Frequency, RAB = 25 k
TPC 12. Gain vs. Frequency vs. Code, RAB = 25 k (Test Circuit 7)
-8-
REV. A
AD5235
0 CODE 200H -10 100H 080H
2.64 2.62 2.60 2.58 VDD = VSS = 5V/0V CODE = 200H TO 1FFH
-30
020H 010H
AMPLITUDE - V
10k 100k FREQUENCY - Hz 1M
-20
GAIN - dB
040H
2.56 2.54 2.52 2.50 2.48 2.46 2.44 2.42 0 10 20 TIME - s 30 40 50
-40
008H 004H
-50
002H 001H
-60 1k
TPC 13. Gain vs. Frequency vs. Code, RAB = 250 k (Test Circuit 7)
80 70
TPC 16. Midscale Glitch Energy, RAB = 25 k, Code 200H to 1 FFH
2.65
2.60 60 RAB = 25k PSRR - -dB 50 40 30 20 10 VDD = 5V 100mV AC VSS = 0V, VA = 5V, VB = 0V MEASURED AT VW WITH CODE = 200 H TA = 25 C 0.1k 1k 10k 100k 1M 10M 2.45 RAB = 250k
AMPLITUDE - V
2.55
2.50
0 0.01k
2.40
0
10
20 TIME - s
30
40
50
FREQUENCY - Hz
TPC 14. PSRR vs. Frequency
TPC 17. Midscale Glitch Energy, RAB = 250 k, Code 200H to 1 FFH
VA = V DD VB = 0 TA = 25 C 0.5V/DIV
VDD VW(D)
5V/DIV
CS
0.5V/DIV
0.5V/DIV
5V/DIV
CLK
5V/DIV
SDI
MIDSCALE
IDD 20mA/DIV
4ms/DIV
50 S/DIV
TPC 15. Power-On Reset, VDD = 2.25 V, Previously Stored Code, D = 2AA H
TPC 18. IDD vs. Time (Save) Program Mode
REV. A
-9-
AD5235
100 VA = VB = OPEN TA = 25 C THEORETICAL - IWB_MAX - mA 10
5V/DIV CS
5V/DIV
CLK
1
5V/DIV
SDI
RAB = 25k
IDD 2mA/DIV 4ms/DIV
0.1 RAB = 250k
*SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION IF INSTRUCTION #0 (NOP) IS EXECUTED IMMEDIATELY AFTER INSTRUCTION #1 (READ EEMEM)
0.01
0
128
256
384
512
640
768
896
1024
CODE - Decimal
TPC 19. IDD vs. Time (Read) Program Mode*
TPC 20. IWB_MAX vs. Code
TEST CIRCUITS
Test Circuits 1 to 10 define the test conditions used in the product specification table.
NC DUT A W B VMS IW VDD V+ VA V+ = V DD A B 10% PSRR (dB) = 20 LOG PSS (%/%) = VMS% VDD%
~
W VMS
(
VMS VDD
)
NC = NO CONNECT
Test Circuit 1. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
DUT A V+ B W VMS V+ = V DD 1LSB = V+/2N
Test Circuit 4. Power Supply Sensitivity (PSS, PSRR)
A VIN OFFSET GND DUT B 5V W OP279 VOUT
OFFSET BIAS
Test Circuit 2. Potentiometer Divider Nonlinearity Error (INL, DNL)
DUT A VMS2 B VMS1 RW = [V MS1 - V MS2]/ IW W VW
Test Circuit 5. Inverting Gain
5V
IW = V DD/R NOMINAL
VIN W OFFSET GND A DUT B
OP279
VOUT
OFFSET BIAS
Test Circuit 3. Wiper Resistance
Test Circuit 6. Noninverting Gain
-10-
REV. A
AD5235
TEST CIRCUITS (continued)
NC +15V W DUT B 2.5V OP42 VOUT VDD DUT VSS GND A W B VCM ICM
A VIN OFFSET GND
-15V
NC NC = NO CONNECT
Test Circuit 7. Gain vs. Frequency
RSW = 0.1V ISW + B ISW VSS TO V DD 0.1V
Test Circuit 9. Common-Mode Leakage Current
A1 VIN NC RDAC1 W1 B1 VSS VDD A2 RDAC2 W2 B2 VOUT
DUT W
CODE = 000H
CTA = 20 LOG [VOUT/V IN] NC = NO CONNECT
Test Circuit 8. Incremental ON Resistance
Test Circuit 10. Analog Crosstalk
OPERATIONAL OVERVIEW
The AD5235 digital potentiometer is designed to operate as a true variable resistor. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratch pad register that allows unlimited changes of resistance settings. The scratch pad register can be programmed with any position setting using the standard SPI serial interface by loading the 24-bit data-word. The format of the data-word is that the first 4 bits are commands, the following 4 bits are addresses, and the last 16 bits are data. Once a specific value is set, this value can be saved into a corresponding EEMEM register. During subsequent power-up, the wiper setting will automatically be loaded at that value. Saving data to the EEMEM takes about 25 ms and consumes approximately 20 mA. During this time, the shift register is locked, preventing any changes from taking place. The RDY pin indicates the completion of this EEMEM saving process. There are also 13 addresses, with 2 bytes each, of user-defined data that can be stored in EEMEM.
OPERATION DETAIL
7. Decrement All One Step 8. Reset EEMEM Setting to RDAC 9. Read EEMEM to SDO 10. Read Wiper Setting to SDO 11. Write Data to RDAC 12. Increment 6 dB 13. Increment All 6 dB 14. Increment One Step 15. Increment All One Step Tables X to XVI provide programming examples by using some of these commands.
Scratch Pad and EEMEM Programming
There are 16 commands that facilitate users' programming needs. Refer to Table II. The commands are: 0. 1. 2. 3. 4. 5. 6. Do Nothing Restore EEMEM Setting to RDAC Save RDAC Setting to EEMEM Save User Data or RDAC Setting to EEMEM Decrement 6 dB Decrement All 6 dB Decrement One Step
The basic mode of setting the digital potentiometer wiper position (programming the scratch pad register) is accomplished by loading the serial data input register with the command 11, the corresponding address, and the data. Since the scratch pad register is a standard logic register, there is no restriction on the number of changes allowed. When the desired wiper position is determined, the user can load the serial data input register with the command 2, which stores the setting into the corresponding EEMEM register. The EEMEM value can be changed at any time or permanently protected by activating the WP command. Table III provides a programming example listing the sequence of serial data input (SDI) words and the corresponding serial data output (SDO) in hexadecimal format.
REV. A
-11-
AD5235
Table I. 24-Bit Serial Data-Word
MSB RDAC
Command Byte 0 0 0 A0 X X X X
Data Byte 1 X X
Data Byte 0
LSB
C3 C2 C1 C0 0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Command bits are C0 to C3. Address bits are A3 to A0. Data bits D0 to D9 are applicable to RDAC wiper register whereas D0 to D15 are applicable to EEMEM register. Command codes are defined in Table II.
Table II. Command Operation Truth Table1, 2, 3
Command Command Byte 0 Data Byte 1 Data Byte 0 Operation Number B23 * * * * * * * * * * * * * * * * B16 B15 * * * * * * B8 B7 * * * * * B0
C3 C2 C1 C0 A3 A2 A1 A0 0 1 0 0 0 0 0 0 0 1 XXX 0 0 0 X A0 X * * * * D9 D8 X****X X****X X X D7 * * * * * D0 X * * * * * * X NOP: Do nothing. See Table XII. X * * * * * * X Write contents of EEMEM(A0) to RDAC(A0) Register. This command leaves device in the read program power state. To return part to the idle state, perform NOP command 0. See Table XII. X******X Save Wiper Setting: Write contents of RDAC(A0) to EEMEM(A0). See Table XI.
2 34 45 55 65 75 8 9
0 0 0 0 0 0 1 1
0 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
0
0
0
A0
X****X
X
A3 A2 A1 A0 0 0 0 A0 X A0 X 0
D15 * * * * D8 X****X X****X X****X X****X X****X X****X X X X X X X
D7 * * * * * D0 Write contents of Serial Register Data Bytes 0 and 1 (total 16-bit) to EEMEM(ADDR). See Table XIV. X******X X******X X******X X******X X******X X******X Decrement 6 dB: Right shift contents of RDAC(A0), register, stops at all "zeros." Decrement all 6 dB: Right shift contents of all RDAC registers, stops at all "zeros." Decrement contents of RDAC(A0) by "one," stops at all "zero." Decrement contents of all RDAC registers by "one," stops at all "zero." RESET: Load all RDACs with their corresponding EEMEM previously saved values. Transfer contents of EEMEM(ADDR) to Serial Register Data Bytes 0 and 1 and previously stored data can be read out from the SDO pin. See Table XV. Transfer contents of RDAC(A0) to Serial Register Data Bytes 0 and 1 and wiper setting can be read out from SDO pin. See Table XVI.
XXX 0 0 0
XXX 0 0 0
A3 A2 A1 A0
10
1
0
1
0
0
0
0
A0
X****X
X
X******X
11 125 135 145 155
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
0 0
0 0
0 0
A0 A0 X A0 X
X * * * * D9 D8 X****X X****X X****X X****X X X X X
D7 * * * * * D0 Write contents of Serial Register Data Bytes 0 and 1 (total 10-bit) to RDAC(A0). See Table X. X******X X******X X******X X******X Increment 6 dB: Left shift contents of RDAC(A0), stops at all "ones." See Table XIII. Increment All 6 dB: Left shift contents of all RDAC registers, stops at all "ones." Increment contents of RDAC(A0) by "one," stops at all "ones." See Table XI. Increment contents of all RDAC registers by "one," stops at all "ones."
XXX 0 0 0
XXX
NOTES 1 The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any command following command 9 or 10, the selected internal register data will be present in data bytes 0 and 1. The commands following 9 and 10 must also be a full 24-bit da ta-word to completely clock out the contents of the serial register. 2 The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding nonvolatile EEMEM register. 3 Execution of the above operations takes place when the CS strobe returns to logic high. 4 Write two data bytes (total 16-bit) to EEMEM. But in the cases of addresses 0 and 1, only the last 10 bits are valid for wiper position setting. 5 The increment, decrement, and shift commands ignore the contents of the shift register data bytes 0 and 1.
-12-
REV. A
AD5235
Table III. Set and Save RDAC with Independent Data to EEMEM Registers
SDI B00100H
SDO XXXXXXH
Action Loads data 100H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. Saves copy of RDAC1 register content into corresponding EEMEM1 register. Loads 200H data into RDAC2 register, Wiper W2 moves to 1/2 full-scale position. Saves copy of RDAC2 register contents into corresponding EEMEM2 register.
20xxxxH B10200H
B00100H 20xxxxH
conditions. Table IV illustrates the operation of the shifting function on the individual RDAC register data bits. Each line going down the table represents a successive shift operation. Note that the left shift 12 and 13 commands were modified such that if the data in the RDAC register is equal to zero, and the data is left shifted, the RDAC register is then set to code 1. Similarly, if the data in the RDAC register is greater than or equal to midscale, and the data is left shifted, then the data in the RDAC register is automatically set to full scale. This makes the left shift function as ideal a logarithmic adjustment as is possible. The right shift 4 and 5 commands will be ideal only if the LSB is zero (i.e., ideal logarithmic--no error). If the LSB is a 1, the right shift function generates a linear half LSB error that translates to a number of bits dependent logarithmic error as shown in Figure 3. The plot shows the error of the odd numbers of bits for AD5235.
Table IV. Detail Left and Right Shift Functions for 6 dB Step Increment and Decrement
21xxxxH
B10200H
At system power-on, the scratch pad register is automatically refreshed with the value previously saved in the corresponding EEMEM register. The factory preset EEMEM value is midscale. The scratch pad register can also be loaded with the contents of the EEMEM register in three different ways. First, executing command 1 retrieves the corresponding EEMEM value. Second, executing command 8 resets both channels' EEMEM values. Finally, pulsing the PR pin also refreshes both EEMEM settings. Operating the hardware control PR function, however, requires a complete pulse signal. When PR goes low, the internal logic sets the wiper at midscale. The EEMEM value will not be loaded until PR returns to high.
EEMEM Protection
Left Shift 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0100 00 0000 1000 00 0001 0000 00 0010 0000 00 0100 0000 00 1000 0000 01 0000 0000 10 0000 0000 11 1111 1111 11 1111 1111
Right Shift 11 1111 1111 01 1111 1111 00 1111 1111 00 0111 1111 00 0011 1111 00 0001 1111 00 0000 1111 00 0000 0111 00 0000 0011 00 0000 0001 00 0000 0000 00 0000 0000 00 0000 0000
Left Shift +6 dB/step
Right Shift +6 dB/step
The write-protect (WP) disables any changes of the scratch pad register contents regardless of the software commands, except that the EEMEM setting can be refreshed and overwrite the WP by using commands 1, 8, and PR pulse. To disable WP, it is recommended to execute a NOP command before returning WP to logic high.
Linear Increment and Decrement Commands
The increment and decrement commands (14, 15, 6, and 7) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to just send an increment or decrement command to the device. The adjustment can be individual or ganged control. For increment command, executing command 14 will automatically move the wiper to the next resistance segment position. The master increment command 15 will move all resistor wipers up by one position.
Logarithmic Taper Mode Adjustment ( 6 dB/Step)
Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each right shift 4 and 5 command execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. The graph in Figure 3 shows plots of Log_Error [i.e., 20 log10 (error/code)] for the AD5235. For example, code 3 Log_Error = 20 log10 (0.5/3) = -15.56 dB, which is the worst case. The plot of Log_Error is more significant at the lower codes.
0
There are four programming commands that provide the logarithmic taper increment and decrement wiper position control by either individually or ganged control. 6 dB increment is activated by commands 12 and 13, and 6 dB decrement is activated by commands 4 and 5. For example, starting at zero scale, executing 12 times of the increment command 12 will move the wiper in 6 dB per step from 0% of the full-scale RAB to the full-scale RAB. The 6 dB increment command doubles the value of the RDAC register contents each time the command is executed. When the wiper position is near the maximum setting, the last 6 dB increment command will cause the wiper to go to the full-scale 1023-code position. Furthermore, 6 dB per increment command will no longer change the wiper position beyond its full scale (see Table IV). 6 dB step increment and decrement are achieved by shifting the bit internally to the left and right, respectively. The following information explains the nonideal 6 dB step adjustment at certain REV. A
-20
dB
-40
-60
-80 0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8 103
0.9
1.0
1.1
CODE - From 1 to 1023 by 2.0
Figure 3. Plot of Log_Error Conformance for Odd Numbers of Bits Only (Even Numbers of Bits Are Ideal)
-13-
AD5235
Push Button Configurable for Previous Command Execution
Another subtle feature of AD5235 is that subsequent CS strobes repeat previous commands. This feature can be used to configure push button control that is particularly useful for increment/ decrement or 6 dB step adjustments.
Using Additional Internal Nonvolatile EEMEM
integer number, and the 8 LSB designates for the decimal number (See Table VI).
Daisy-Chain Operation
The AD5235 contains additional internal user storage registers (EEMEM) for saving constants and other 16-bit data. Table V provides an address map of the internal storage registers shown in the functional block diagram as EEMEM1, EEMEM2, and 26 bytes (13 addresses 2 bytes each) of USER EEMEM.
Table V. EEMEM Address Map
EEMEM Number 1 2 3 4 : 15 16
Address 0000 0001 0010 0011 : 1110 1111
EEMEM Content For RDAC11, 2 RDAC2 USER13 USER2 : USER13 RAB1_ACTUAL4
The serial data output pin (SDO) can be used to read out the contents of the wiper setting and EEMEM value under commands 10 and 9, respectively. If these commands are not used, SDO can be used for daisy-chaining multiple devices for simultaneous operations (see Figure 4). The SDO pin contains an open-drain N-Ch FET and requires a pull-up resistor if SDO function is used. Users need to tie the SDO pin of one package to the SDI pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO-SDI interface may induce time delay to the subsequent devices (see Figure 4). If two AD5235s are daisy-chained, this requires a total of 48 bits of data. The first 24 bits (formatted 4-bit command, 4-bit address, and 16-bit data) go to U2, and the second 24 bits with the same format go to U1. The CS should be kept low until all 48 bits are clocked into their respective serial registers. The CS is then pulled high to complete the operation.
VDD
NOTES 1 RDAC data stored in EEMEM locations are transferred to their corresponding RDAC Register at power-on, or when commands 1, 8, and PR are executed. 2 Execution of command 1 leaves the device in the Read Mode power consumption state. After the last command 1 is executed, the user should perform a NOP, command 0 to return the device to the low power idling state. 3 USER are internal nonvolatile EEMEM registers available to store and retrieve constants and other 16-bit information using commands 3 and 9, respectively. 4 Read only.
AD5235
U1 MOSI C SCLK SS SDI SDO
RP 2.2k SDI
AD5235
U2 SDO
CS
CLK
CS
CLK
Figure 4. Daisy-Chain Configuration
DIGITAL INPUT/OUTPUT CONFIGURATION
Calculating Actual End-to-End Terminal Resistance
The resistance tolerance is stored in the EEMEM register during factory testing. The actual end-to-end resistance can therefore be calculated, which is valuable for calibration, tolerance matching, and precision applications. Notice this value is read only and the RAB2 matches with RAB1 of typically 0.1%. The resistance tolerance in percentage is contained in the last 16 bits of data in the EEMEM Register 15. The format is the sign magnitude binary format with the MSB designate for sign (0 = positive and 1 = negative), the next 7 MSB designates for the
All digital inputs are ESD protected. Digital inputs are high impedance and can be driven directly from most digital sources. Active at logic low, PR and WP should be biased to VDD if they are not used. There are no internal pull-up resistors on any digital input pin. To avoid floating digital pins that may cause false triggering in the noisy environment, pull-up resistors should be added. This is applicable in cases where the device will be detached from the driving source once it is programmed.
Table VI. Calculating End-to-End Terminal Resistance
Bit Sign Mag
D15 Sign Sign
D14 26
D13 25
D12 24
D11 23
D10 22
D9 21
D8 20
D7
D6 2-2
D5 2-3
D4 2-4
D3 2-5
D2 2-6
D1 2-7
D0 2-8
*
2-1
7 Bits for Integer Number
Decimal Point
8 Bits for Decimal Number
For example, if RAB_RATED = 250 k and the data in the SDO shows XXXX XXXX 0001 1100 0000 1111, RAB_ACTUAL can be calculated as follows: MSB: 0 = Positive Next 7 MSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 2-8 = 0.06 % Tolerance = 28.06% Hence, RAB_ACTUAL = 320.15 k
-14-
REV. A
AD5235
The SDO and RDY pins are open-drain digital outputs. Similarly, pull-up resistors are needed if these functions are used. To optimize the speed and power trade-off, use 2.2 k pull-up resistors. The equivalent serial data input and output logic is shown in Figure 5. The open-drain output SDO is disabled whenever chip select CS is logic high. ESD protection of the digital inputs is shown in Figures 6a and 6b.
PR VALID COMMAND COUNTER WP
The last command prior to a period of no programming activity should be applied with the no operation (NOP), command 0. It is recommended to do so to ensure minimum power consumption in the internal logic circuitry. The SPI interface can be used in two slave modes CPHA = 1, CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to the control bits that dictate the SPI timing in these MicroConverter(R) and microprocessor parts: ADUC812/824, M68HC11, and MC68HC16R1/916R1.
TERMINAL VOLTAGE OPERATING RANGE
COMMAND PROCESSOR AND ADDRESS DECODE
5V
RPULLUP CLK SERIAL REGISTER (FOR DAISY CHAIN ONLY) SDO CS SDI GND
The AD5235 positive VDD and negative VSS power supply defines the boundary conditions for proper three-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or VSS will be clamped by the internal forward biased diodes (see Figure 7).
VDD
Figure 5. Equivalent Digital Input-Output Logic
VDD
A W B
LOGIC PINS
INPUTS 300
VSS
Figure 7. Maximum Terminal Voltages Set by VDD and VSS
GND
Figure 6a. Equivalent ESD Digital Input Protection
VDD
INPUT 300 WP
The ground pin of the AD5235 device is primarily used as a digital ground reference. To minimize the digital ground bounce, the AD5235 ground terminal should be joined remotely to the common ground (see Figure 8). The digital input control signals to the AD5235 must be referenced to the device ground pin (GND) and must satisfy the logic level defined in the specification table of this data sheet. An internal level shift circuit ensures that the commonmode voltage range of the three terminals extends from VSS to VDD, regardless of the digital input level. In addition, VAB, VWA, and VWB have no polarity constraint. Their magnitudes are bounded by their applied voltages and VDD - VSS, whichever is the smallest.
Power-Up Sequence
GND
Figure 6b. Equivalent WP Input Protection
SERIAL DATA INTERFACE
The AD5235 contains a 4-wire SPI-compatible digital interface (SDI, SDO, CS, and CLK). The 24-bit serial word must be loaded with MSB first, and the format of the word is shown in Table I. The command bits (C0 to C3) control the operation of the digital potentiometer according to the command shown in Table II. A0 to A3 are assigned for address bits. A0 is used to address RDAC1 or RDAC2. Addresses 2 to 14 are accessible by users. Address 15 is reserved for factory usage. Table V provides an address map of the EEMEM locations. The data bits (D0 to D9) are the values that are loaded into the RDAC registers at command 11. The data bits (D0 to D15) are the values that are loaded into the EEMEM registers at command 3.
MicroConverter is a registered trademark of Analog Devices, Inc.
Since there are diodes to limit the voltage compliance at terminals A, B, and W (see Figure 7), it is important to power VDD/VSS first before applying any voltage to terminals A, B, and W. Otherwise, the diode will be forward biased such that VDD/VSS will be powered unintentionally. For example, applying 5 V across terminals A and B prior to VDD will cause the VDD terminal to exhibit 4.3 V. It is not destructive to the device, but it may affect the rest of the user's system. As a result, the ideal power-up sequence is in the following order: GND, VDD/VSS, digital Inputs, and VA, VB, and VW. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VDD/VSS. Regardless of the power-up sequence and the ramp rates of the power supplies, once VDD/VSS are powered, the power-on reset activates, which retrieves EEMEM saved values to the RDAC registers (see TPC 15).
REV. A
-15-
AD5235
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum-lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 F to 0.1 F disc or chip ceramic capacitors. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance (Figure 8).
AD5235
VDD C3 10 F C4 10 F + + C1 0.1 F C2 0.1 F VDD
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation
The nominal resistance of the RDAC between terminals A and B, RAB, is available with 25 k and 250 k with 1024 positions (10-bit resolution). The final digits of the part number determine the nominal resistance value, e.g., 25 k = 25; 250 k = 250. The 10-bit data-word in the RDAC latch is decoded to select one of the 1024 possible settings. The following discussion describes the calculation of resistance RWB at different codes of a 25 k part. The wiper's first connection starts at the B terminal for data 000H. RWB(0) is 50 because of the wiper resistance, and it is independent of the nominal resistance. The second connection is the first tap point where RWB(1) becomes 24.4 + 50 = 74.4 for data 001H. The third connection is the next tap point representing RWB(2) = 48.8 + 50 = 98.8 for data 002H and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB(1023) = 25026 . See Figure 9 for a simplified diagram of the equivalent RDAC circuit. When RWB is used, the A terminal can be left floating or tied to the wiper.
100
VSS
VSS GND
Figure 8. Power Supply Bypassing
The patent pending RDAC contains multiple strings of equal resistor segments with an array of analog switches that acts as the wiper connection. The number of positions is the resolution of the device. The AD5235 has 1024 connection points, allowing it to provide better than 0.1% setability resolution. Figure 9 shows an equivalent structure of the connections between the three terminals of the RDAC. The SWA and SWB will always be on, while one of the switches SW(0) to SW(2N - 1) will be on one at a time depending on the resistance position decoded from the data bits. Since the switch is not ideal, there is a 50 wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature. The lower the supply voltage or the higher the temperature, the higher the resulting wiper resistance. Users should be aware of the wiper resistance dynamics if accurate prediction of the output resistance is needed.
SWA A SW(2N-1)
RWA(D), RWB(D) - % Rwf
RDAC STRUCTURE
RWA 75
RWB
50
25
0
0
256
512 CODE - Decimal
768
1023
Figure 10. RWA(D) and RWB(D) vs. Decimal Code
The general equation that determines the programmed output resistance between Wx and Bx is: R WA ( D ) = D x RAB + R W 1024 (1)
RDAC WIPER REGISTER AND DECODER
RS
W SW(2N- 2)
Where D is the decimal equivalent of the data contained in the RDAC register, RAB is the nominal resistance between terminals A and B, and RW is the wiper resistance. For example, the following output resistance values will be set for the following RDAC latch codes (applies to RAB = 25 k digital potentiometers).
Table VIII. RWB(D) at Selected Codes (RAB = 25 k )
RS
SW(1)
RS RS = RAB / 2N DIGITAL CIRCUITRY OMITTED FOR CLARITY
SW(0)
SWB B
D (DEC) 1023 512 1 0 250 k 244 -16-
RWB(D) () 25026 12550 74.4 50
Output State Full Scale Midscale 1 LSB Zero Scale (Wiper Contact Resistance)
Figure 9. Equivalent RDAC Structure
Table VII. Nominal Individual Segment Resistor Values
Device Resolution 1024-Step
25 k 24.4
REV. A
AD5235
Note that in the zero-scale condition, a finite wiper resistance of 50 is present. Care should be taken to limit the current flow between W and B in this state to no more than 20 mA to avoid degradation or possible destruction of the internal switches. Like the mechanical potentiometer the RDAC replaces, the AD5235 parts are totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. Figure 10 shows the symmetrical programmability of the various terminal connections. When RWA is used, the B terminal can be left floating or tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: RWA ( D ) = 1024 - D x RAB + RW 1024 (2)
PROGRAMMING EXAMPLES
The following programming examples illustrate the typical sequence of events for various features of the AD5235. Users should refer to Table II for the commands and data-word format. The command numbers, addresses, and data appearing at the SDI and SDO pins are displayed in hexadecimal format in the following examples.
Table X. Scratch Pad Programming
SDI B00100H B10200H
SDO XXXXXXH B00100H
Action Loads data 100H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. Loads data 200H into RDAC2 register, Wiper 2 moves to 1/2 full-scale position.
For example, the following output resistance values will be set for the following RDAC latch codes (applies to RAB = 25 k digital potentiometers). SDI
Table IX. RWA(D) at Selected Codes (RAB = 25 k )
Table XI. Incrementing RDAC Followed by Storing the Wiper Setting to EEMEM
SDO
Action
D (DEC) 1023 512 1 0
RWA(D) () 74.4 12550 25026 25050
B00100H Output State Full Scale Midscale 1 LSB Zero Scale (Wiper Contact Resistance) E0XXXXH E0XXXXH 20XXXXH
The typical distribution of RAB from channel-to-channel matches to 0.2% within the same package. Device-to-device matching is process lot dependent upon the worst case of 30% variation. On the other hand, the change in RAB with temperature has a 35 ppm/C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
XXXXXXH Loads data 100H into RDAC1 register, Wiper W1 moves to 1/4 full-scale position. B00100H Increments RDAC1 register by one to 101H. E0XXXXH Increments RDAC1 register by one to 102H. Continue until desired wiper position reached. XXXXXXH Saves RDAC1 data into EEMEM1. Optionally tie WP to GND to protect EEMEM values.
Table XII. Restoring EEMEM Values to RDAC Registers
The digital potentiometer can be configured to generate an output voltage at the wiper terminal that is proportional to the input voltages applied to terminals A and B. For example, connecting terminal A to 5 V and terminal B to ground produces an output voltage at the wiper that can be any value from 0 V to 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 2N position resolution of the potentiometer divider. Since AD5235 can also be supplied by dual supplies, the general equation defining the output voltage at VW with respect to ground for any given input voltages applied to terminals A and B is: D VW ( D ) = x VAB + VB 1024 (3)
EEMEM values for RDACs can be restored by: Power-on or Strobing PR pin or two different commands shown below SDI SDO Action 10XXXXH XXXXXXH Restores EEMEM1 value to RDAC1 register. 00XXXXH 10XXXXH NOP. Recommended step to minimize power consumption. 8XXXXXH 00XXXXH Reset EEMEM1 and EEMEM2 values to RDAC1 and RDAC2 registers, respectively.
Table XIII. Using Left Shift by One to Increment 6 dB Steps
SDI
SDO
Action
Equation 3 assumes VW is buffered so that the effect of wiper resistance is nulled. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here, the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the drift improves to 15 ppm/C. There is no voltage polarity restriction between terminals A, B, and W as long as the terminal voltage (VTERM) stays within VSS < VTERM < VDD.
C0XXXXH XXXXXXH Moves wiper 1 to double the present data contained in RDAC1 register. C1XXXXH C0XXXXH Moves wiper 2 to double the present data contained in RDAC2 register.
REV. A
-17-
AD5235
Table XIV. Storing Additional User Data in EEMEM Gain Control Compensation
SDI 32AAAAH
SDO
Action
A digital potentiometer is commonly used in gain control, such as in the noninverting gain amplifier shown in Figure 12.
C2 2.2pF R2 250k B A R1 47k C1 11pF Vi U1 W
335555H
XXXXXXH Stores data AAAAH into spare EEMEM location USER1. (Allowable to address in 13 locations with maximum 16 bits of data.) 32AAAAH Stores data 5555H into spare EEMEM location USER2. (Allowable to address 13 locations with maximum 16 bits of data.)
VO
Table XV. Reading Back Data From Various Memory Locations
SDI
SDO
Action
Figure 12. Typical Noninverting Gain Amplifier
92XXXXH XXXXXXH Prepares data read from USER1 location. 00XXXXH 92AAAAH NOP command 0 sends 24-bit word out of SDO where the last 16 bits contain the contents of USER1 location. NOP command ensures device returns to idle power dissipation state.
Table XVI. Reading Back Wiper Setting
SDI
SDO
Action
Notice the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node; it introduces a zero for the 1/O term with 20 dB/dec, whereas a typical op amp GBP has -20 dB/dec characteristics. A large R2 and finite C1 can cause this zero's frequency to fall well below the crossover frequency. Hence, the rate of closure becomes 40 dB/dec and the system has 0 phase margin at the crossover frequency. The output may ring or oscillate if an input is a rectangular pulse or step functions. Similarly, it is also likely to ring when switching between two gain values; this is equivalent to a step change at the input. Depending on the op amp GBP, reducing the feedback resistor may extend the zero's frequency far enough to overcome the problem. A better approach is to include a compensation capacitor, C2, to cancel the effect caused by C1. Optimum compensation occurs when R1 C1 = R2 C2. This is not an option because of the variation of R2. As a result, one may use the relationship above and scale C2 as if R2 is at its maximum value. Doing so may overcompensate and compromise the performance when R2 is set at low values. On the other hand, it will avoid the ringing or oscillation at the worst case. For critical applications, C2 should be found empirically to suit the need. In general, C2 in the range of a few pF to no more than a few tenths of pF is usually adequate for the compensation. Similarly, there are W and A terminal capacitances connected to the output (not shown). Fortunately their effect at this node is less significant and the compensation can be avoided in most cases.
High Voltage Operation
XXXXXXH Sets RDAC1 to midscale. B00200H C0XXXXH B00200H Doubles RDAC1 from midscale to full scale. A0XXXXH C0XXXXH Prepares reading wiper setting from RDAC1 register. Readback full-scale value from RDAC1 XXXXXXH A003FFH register. Analog Devices offers a user-friendly AD5235EVAL evaluation kit that can be controlled by a personal computer through the printer port. The driving program is self-contained, so no programming languages or skills are needed.
APPLICATIONS Bipolar Operation From Dual Supplies
The AD5235 can be operated from dual supplies 2.5 V, which enables control of ground referenced ac signals or bipolar operation. AC signals, as high as VDD /VSS, can be applied directly across terminals A to B with the output taken from terminal W. See Figure 11 for a typical circuit connection.
+2.5V VDD C GND SS SCLK MOSI CS CLK SDI VDD A W GND B VSS 1.25V p-p 2.5V p-p
AD5235
D = MIDSCALE
As shown in the previous example, the digital potentiometer can be placed directly in the feedback or input path of an op amp for gain control, provided that the voltage across terminals A-B, W-A, or W-B does not exceed |5 V|. When high voltage gain is needed, users should set a fixed gain in an op amp and let the digital potentiometer control the adjustable input. Figure 13 shows a simple implementation. Similarly, a compensation capacitor C may be needed to dampen the potential ringing whenever the digital potentiometer changes steps. This effect is prominent when stray capacitance at the inverting node is augmented by a large feedback resistor. In general, a picofarads capacitor C is adequate to combat the problem.
-2.5V
Figure 11. Bipolar Operation from Dual Supplies
-18-
REV. A
AD5235
C R 2R 15V 5V A1 A W V+ VO V- 0V TO 15V
Table XVII. Result of Bipolar Gain Amplifier
D 0 256 512 768 1023
R1 = , R2 = 0 -1 -0.5 0 0.5 0.992
R1 = R2 -2 -1 0 1 1.984
R2 = 9R1 -10 -5 0 5 9.92
AD5235
B
Figure 13. 15 V Voltage Span Control
Programmable Voltage Reference
10-Bit Bipolar DAC
For voltage divider mode operation, Figure 14, it is common to buffer the output of the digital potentiometer unless the load is much larger than RWB. Not only does the buffer serve the purpose of impedance conversion, it also allows a heavier load to be driven.
5V 1 U1 VIN VOUT GND 2 AD1582 3
AD5235
A B W
5V
If we change the circuit in Figure 15 with the input taken from a precision reference, set U1 to midscale, and configure A2 as a buffer, a 10-bit bipolar DAC can be realized (Figure 16). Compared to the conventional DAC, this circuit offers comparable resolution but not the precision because of the wiper resistance effects. Degradation of the nonlinearity and temperature coefficient is prominent near the low values of the adjustment range. On the other hand, this circuit offers a unique nonvolatile memory feature that in some cases outweighs the shortfall of nonprecision. Without considering the wiper resistance, the output of this circuit is approximately:
2D2 VO = - 1 x VREF 1024
+2.5V
V+ AD8601 V- A1
VO
(6)
Figure 14. Programmable Voltage Reference
Bipolar Programmable Gain Amplifier
Vi 2 U3 VIN VOUT TRIM GND 6 5 +2.5VREF
U2 W2 B2 A1 W1 U1 U1 = MIDSCALE - V+ V- A2 B1 +2.5V
+
V+ V- A2 -2.5V VO
AD8552
-
For applications requiring bipolar gain, Figure 15 shows one implementation. Digital potentiometer U1 sets the adjustment range. The wiper voltage VW2 can therefore be programmed between Vi and -KVi at a given U2 setting. Configure A2 as a noninverting amplifier that yields a transfer function
VO R D = 1 + 2 x 2 x (1 + K ) - K Vi R1 1024
-2.5VREF
ADR421
AD8552
U1 = U2 = AD5235 A1 -2.5V +
(4)
where K is the ratio of RWB1/RWA1 set by U1.
VDD
Figure 16. 10-Bit Bipolar DAC
Programmable Voltage Source with Boosted Output
VO R2 C
AD5235
U2 A2
+ W2 B2
V+ V- VSS
OP2177
- A2
For applications requiring high current adjustment, such as a laser diode driver or turnable laser, a boosted voltage source can be considered (Figure 17).
VS VBIAS R1 10k A U1 B P1 SIGNAL CC W + V+ A1 V- N1 LD RBIAS IBIAS
Vi
A1
B1 W1 - VDD V+ V-
-kVi R1
5V
AD5235
U1
OP2177
+ A1
VSS
-
Figure 15. Bipolar Programmable Gain Amplifier
In the simpler (and much more usual) case, where K = 1, VO simplifies to:
R 2D2 VO = 1 + 2 - 1 x Vi R1 1024
U1 = 1/2 AD5235 A1 = AD8601, AD8605, AD8541 P1 = FDP360P, FDV302P N1 = FDV301N, 2N7002
Figure 17. Programmable Boosted Voltage Source
(5)
Table XVII shows the result of adjusting D2, with A2 configured as a unity gain, a gain of 2, and a gain of 10. The result is a bipolar amplifier with linearly programmable gain and 1024-step resolution. REV. A
In this circuit, the inverting input of the op amp forces the VBIAS to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the P-Ch FET P1. The N-Ch FET N1 simplifies the op amp driving requirement. A1 needs to be rail-to-rail input type. Resistor R1 is needed
-19-
AD5235
to prevent P1 from not turning off once it is on. The choice of R1 is a balance between the power loss of this resistor and the output turn off time. N1 can be any general-purpose signal FET; on the other hand, P1 is driven in the saturation state and therefore its power handling must be adequate to dissipate (VS - VBIAS) IBIAS power. This circuit can source maximum of 100 mA at 5 V supply. Higher current can be achieved with P1 in larger package. Note a single N-Ch FET can replace P1, N1, and R1 altogether. However, the output swing will be limited unless separate power supplies are used. For precision applications, a voltage reference, such as ADR423, ADR292, and AD1584, can be applied at the input of the digital potentiometer.
Programmable 4 to 20 mA Current Source
R1 150k R2 15k +15V - +2.5V +15V V+ R2B 50 C1 10pF
OP2177
+ V- C2 10pF R1 150k -15V R2A 14.95k VL RL 500 IL A2
AD5235
A B W + V+
OP2177
- V- A1
-2.5V
-15V
Figure 19. Programmable Bidirectional Current Source
A programmable 4 to 20 mA current source can be implemented with the circuit shown in Figure 18. REF191 is a unique low supply headroom and high current handling precision reference that can deliver 20 mA at 2.048 V. The load current is simply the voltage across terminals B to W of the digital potentiometer divided by RS:
R2B in theory can be made as small as needed to achieve the current needed within A2 output current driving capability. In this circuit, OP2177 can deliver 5 mA in either direction and the voltage compliance approaches +15 V. Without the additions of C1 and C2, the output impedance (looking into VL) can be shown as:
V xD I L = REF RS
+5V 2 VIN 3 SLEEP VOUT 6 U1 0 TO (2.048 + VL) B C1 1F A +5V -
(7)
ZO =
' R1R2 - R1' ( R2 A + R2 B )
R1' R2 B ( R1 + R2 A )
(9)
This output impedance can be infinite if resistors R1 and R2 match precisely with R1 and R2A + R2B, respectively, which is desirable. On the other hand, it can be negative if the resistors are not matched and cause oscillation. As a result, C1 and C2, in the range of a few pF, are needed to prevent the oscillation.
Programmable Low-Pass Filter
W RS 102
REF191
GND 4
AD5235
-2.048V TO VL
V+ U2
In A to D conversion applications, it is common to include an antialiasing filter to band limit the sampling signal. The dual channel AD5235 can therefore be used to construct a second order Sallen key low-pass filter (Figure 20). The design equations are:
VL
OP1177
+ RL 100 V- -5V
IL
VO = Vi
wf wf 2 S2+ S + wf Q
1 R 1 R 2 C 1 C2
2
(10)
Figure 18. Programmable 4 mA to 20 mA Current Source
The circuit is simple but beware of two things. First, dual-supply op amps are ideal because the ground potential of REF191 can swing from -2.048 V at zero scale to VL at full scale of the potentiometer setting. Although the circuit works under single supply, the programmable resolution of the system will be reduced. Second, the voltage compliance at VL is limited to 2.5 V or equivalently a 125 load. Should higher voltage compliance be needed, users may consider digital potentiometers AD5260, AD5280, and AD7376. Figure 19 shows an alternate circuit for high voltage compliance.
Programmable Bidirectional Current Source
O =
(11)
Q=
1 1 + R1C1 R2C2
(12)
For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution (see Figure 19). If the resistors are matched, the load current is:
R 2 A+ R 2B R1 IL = x VW R 2B
Users can first select some convenient values for the capacitors. To achieve maximally flat bandwidth where Q = 0.707, let C1 be twice the size of C2 and let R1 = R2. As a result, the user can adjust R1 and R2 concurrently to the same setting to achieve the desirable bandwidth.
C1 +2.5V Vi A R1 W R R B A R2 W C2 B W + V+ VO
(8)
AD8601 - V- U1 -2.5V
ADJUSTED CONCURRENTLY
Figure 20. Sallen Key Low Pass Filter
-20-
REV. A
AD5235
Programmable Oscillator Optical Transmitter Calibration with ADN2841
In a classic Wien-bridge oscillator, Figure 21, the Wien network (R, R, C, C) provides positive feedback, while R1 and R2 provide negative feedback. At the resonant frequency, fO, the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. With R = R, C = C, and R2 = R2A /(R2B + Rdiode), the oscillation frequency is: O = 1 RC or fO = 1 2RC (13)
Together with the multirate 2.7 Gbps laser diode driver ADN2841, the AD5235 forms an optical supervisory system where the dual digital potentiometers can be used to set the laser average optical power and extinction ratio (Figure 22). AD5235 is particularly ideal for the optical parameter settings because of its high resolution and superior temperature coefficient characteristics. The ADN2841 is a 2.7 Gbps laser diode driver that uses a unique control algorithm to manage both the laser average power and extinction ratio after the laser initial factory calibration. It stabilizes the laser data transmission by continuously monitoring its optical power and correcting the variations caused by temperature and the laser degradation over time. In ADN2841, the IMPD monitors the laser diode current. Through its dual loop power and extinction ratio control, calibrated by AD5235 dual RDACs, the internal driver controls the bias current IBIAS and consequently the average power. It also regulates the modulation current, IMODP, by changing the modulation current linearly with slope efficiency. Any changes in the laser threshold current or slope efficiency are therefore compensated. As a result, this optical supervisory system minimizes the laser characterization efforts and therefore enables designers to apply comparable lasers from multiple sources.
VCC VCC
where R is equal to RWA such that: R= 1024 - D RAB 1024 (14)
At resonance, setting:
R2 =2 R1
(15)
balances the bridge. In practice, R2 /R 1 should be set slightly larger than 2 to ensure the oscillation can start. On the other hand, the alternate turn-on of the diodes D1 and D2 ensures that R2 /R1 are smaller than 2, momentarily stabilizing the oscillation. Once the frequency is set, the oscillation amplitude can be tuned by R2B since: 2 V = I D R2 B + VD 3O (16)
AD5235
RDAC1 CS CLK SDI
VP C R 25k B
DIN
IMPD W1
VO, ID, and VD are interdependent variables. With proper selection of R2B, an equilibrium will be reached such that Vwf converges. R2B can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to saturate the output.
FREQUENCY ADJUSTMENT B R 25k A W
ADN2841
EEMEM CONTROL
A1 B1 RDAC2 A2 B2 W2
PSET
IMODP IBIAS
C 2.2nF
A 2.2nF W +2.5V + U1 V+
OP1177 - V- R = R = AD5235 R2B = AD5231 D1 = D2 = 1N4148 -2.5V R2B 10k B W R1 1k A R2A 2.1k D1 D2
VO
DIN DINQ IDTONE
Figure 22. Optical Supervisory System
Resistance Scaling
AMPLITUDE ADJUSTMENT
AD5235 offers either 25 k or 250 k nominal resistance. For users who need lower resistance but must still maintain the number of step adjustments, they can parallel multiple devices. Figure 23 shows a simple scheme of paralleling both channels of RDACs. In order to adjust half of the resistance linearly per step, users need to program both RDACs coherently with the same settings.
Figure 21. Programmable Oscillator with Amplitude Control
In both circuits in Figures 20 and 21, the frequency tuning requires both RDACs to be adjusted concurrently to the same settings. Since the two channels will be adjusted one at a time, an intermediate state will occur that may not be acceptable for certain applications. Of course, the increment/decrement commands 5, 7, 13, and 15 can all be used. Different devices can also be used in daisy-chain mode so that parts can be programmed to the same settings simultaneously.
A1 B1 W1
A2 B2 W2
Figure 23. Reduce Resistance by Half with Linear Adjustment Characteristics
REV. A
-21-
IDTONE
EEMEM
ERSET
DINQ
AD5235
Applicable only to the voltage divider mode operation, a much lower resistance can be achieved by paralleling a discrete resistor as shown in Figure 24. The equivalent resistance becomes: R WB eq = D (R //R ) + R W 1024 1 2 (17)
R1* - B R2 A W C1
AD8601
Vi + U1
VO
D R WA eq = 1 - R 1//R 2 + R W 1024
(
)
(18)
*REPLACED WITH ANOTHER CHANNEL OF RDAC
A
Figure 26. Linear Gain Control with Tracking Resistance Tolerance, Drift, and Temperature Coefficient.
W
R2
R1
B R2 << R1
Notice the circuit in Figure 27 can track the tolerance, temperature coefficient, and drift in this particular application. The characteristic of the transfer function is, however, a pseudo-logarithmic, rather than linear, gain function.
ARB W C1
Figure 24. Lowering the Nominal Resistance
Figures 23 and 24 show that the digital potentiometers change steps linearly. On the other hand, pseudo log taper adjustment is usually preferred in applications like audio control. Figure 25 shows another way of resistance scaling. In this approach, the smaller the R2 with respect to RAB, the more the pseudo log taper characteristic behaves. The equation is approximated as:
-
AD8601
Vi + U1
VO
R eq =
D x RAB + 51200 D x RAB + 51200 + 1024 x R
A1 W1 B1 R
(19)
Figure 27. Nonlinear Gain Control with Tracking Resistance Tolerance and Drift
RDAC CIRCUIT SIMULATION MODEL
Figure 25. Resistor Scaling with Pseudo Log Adjustment Characteristics
The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider, the -3 dB bandwidth of the AD5235 (25 k resistor) measures 125 kHz at half scale. TPC 11 provides the large signal BODE plot characteristics of the two available resistor versions, 25 k and 250 k. A parasitic simulation model is shown in Figure 28.
RDAC 25k A B CB 11pF CA 11pF
Users should also be aware of the need for tolerance matching as well as for temperature coefficient matching of the components.
RESISTANCE TOLERANCE, DRIFT, AND TEMPERATURE COEFFICIENT MISMATCH CONSIDERATIONS
In the rheostat mode operation, such as gain control (Figure 26), the tolerance mismatch between the digital potentiometer and the discrete resistor can cause repeatability issues among various systems. Because of the inherent matching of the silicon process, it is practical to apply the dual channel device in this type of application. As such, R1 can be replaced by one of the channels of the digital potentiometer and programmed to a specific value. R2 can be used for the adjustable gain. Although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between R1 and R2. In addition, this approach also tracks the resistance drift over time. As a result, these less than ideal parameters become less sensitive to the system variations.
80pF W
Figure 28. RDAC Circuit Simulation Model (RDAC = 25 k)
Listing I provides a macro model net list for the 25 k RDAC.
Listing I. Macro Model Net List for RDAC
.PARAM D = 1024, RDAC = 25E3 * .SUBCKT DPOT (A, W, B) * CA A 0 11E-12 RWA A W {(1-D/1024) RDAC + 50} CW W 0 80E-12 RWB W B {D/1024 RDAC + 50} CB B 0 11E-12 * .ENDS DPOT
-22-
REV. A
AD5235
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE* Part Number AD5201 Number of VRs per Package 1 Terminal Voltage Range (V) 3, 5.5 Interface Data Control 3-Wire Nominal Resistance (k ) 10, 50 Resolution Power Supply (No. of Wiper Current Positions) (IDD) ( A) Packages 33 40 MSOP-10
Comments Full AC Specs, Dual Supply, Power-OnReset, Low Cost No Rollover, Power-On-Reset Single 28 V or Dual 15 V Supply Operation Full AC Specs, Dual Supply, Power-On-Reset Full AC Specs 5 V to 15 V or 5 V Operation, TC < 50 ppm/C I2C Compatible, TC < 50 ppm/C Nonvolatile Memory, Direct Program, I/D, 6 dB Settability No Rollover, Stereo, Power-On-Reset, TC < 50 ppm/C Full AC Specs, nA Shutdown Current Full AC Specs, Dual Supply, Power-OnReset, SDO Nonvolatile Memory, Direct Program, I/D, 6 dB Settability Nonvolatile Memory, Direct Program, TC < 50 ppm/C I2C-Compatible, TC < 50 ppm/C 5 V to 15 V or 5 V Operation, TC < 50 ppm/C
AD5220 AD7376
1 1
5.5 15, 28
UP/DOWN 3-Wire
10, 50, 100 10, 50, 100, 1000 10, 50
128 128
40 100
PDIP, SO-8, MSOP-8 PDIP-14, SOL-16, TSSOP-14 MSOP-10 SO-8 TSSOP-14
AD5200 AD8400 AD5260
1 1 1
3, 5.5 5.5 5, 15
3-Wire 3-Wire 3-Wire
256
40 5 60
1, 10, 50, 100 256 20, 50, 200 256
AD5241 AD5231
1 1
3, 5.5 2.75, 5.5
2-Wire 3-Wire
10, 100, 1000 10, 50, 100
256 1024
50 10
SO-14, TSSOP-14 TSSOP-16
AD5222
2
3, 5.5
UP/DOWN
10, 50, 100, 1000 1, 10, 50, 100 10, 50, 100
128
80
SO-14, TSSOP-14 PDIP, SO-14, TSSOP-14 TSSOP-14
AD8402 AD5207
2 2
5.5 3, 5.5
3-Wire 3-Wire
256 256
5 40
AD5232
2
2.75, 5.5
3-Wire
10, 50, 100
256
10
TSSOP-16
AD5235
2
2.75, 5.5
3-Wire
25, 250
1024
6
TSSOP-16
AD5242 AD5262
2 2
3, 5.5 5, 15
2-Wire 3-Wire
10, 100, 1000 20, 50, 200
256 256
50 60
SO-16, TSSOP-16 TSSOP-16
AD5203 AD5233
4 4
5.5 2.75, 5.5
3-Wire 3-Wire
10, 100 10, 50, 100
64 64
5 10
PDIP, SOL-24, Full AC Specs, nA TSSOP-24 Shutdown Current TSSOP-24 Nonvolatile Memory, Direct Program, I/D, 6 dB Settability
AD5204 AD8403 AD5206
*
4 4 6
3, 5.5 5.5 3, 5.5
3-Wire 3-Wire 3-Wire
10, 50, 100
256
60 5 60
PDIP, SOL-24, Full AC Specs, Dual TSSOP-24 Supply, Power-On-Reset PDIP, SOL-24, Full AC Specs, nA TSSOP-24 Shutdown Current PDIP, SOL-24, Full AC Specs, Dual TSSOP-24 Supply, Power-On-Reset
1, 10, 50, 100 256 10, 50, 100 256
For the most current information on digital potentiometers, check the website at: www.analog.com/DigitalPotentiometers
REV. A
-23-
AD5235
OUTLINE DIMENSIONS 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)
Dimensions shown in millimeters
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 1.20 MAX 0.20 0.09 SEATING PLANE 8 0 0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153AB
Revision History
Location 08/02--Data Sheet changed from REV. 0 to REV. A. Page
Change to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Change to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to Calculating Actual End-to-End Terminal Resistance section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
-24-
REV. A
PRINTED IN U.S.A.
C02816-0-8/02(A)

▲Up To Search▲

Price & Availability of AD5235

	To Download AD5235 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .